1. Field of the Invention
The present invention relates to a semiconductor die and, more particularly, to a semiconductor die with aluminum-spiked heat pipes.
2. Description of the Related Art
Conventional semiconductor die have many advantages, but also suffer from a number of problem areas. One problem area is the removal of heat from the substrate of the die. The high current circuits of present-generation integrated circuits can generate significant amounts of heat in the substrate which, if not removed, can damage or erroneously bias adjacent circuits. One approach to reduce the heat in the substrate of an integrated circuit is to use heat pipes that are formed in the backside of the substrate.
FIG. 1 shows a cross-sectional diagram that illustrates a prior-art semiconductor die 100 with backside heat pipes. As shown in FIG. 1, die 100 has a conventional structure that includes a p− semiconductor substrate 110, and a number of shallow trench isolation (STI) regions that are formed in substrate 110. Die 100 also includes a p-well 112 and an n-well 114 that are formed in substrate 110. P− well 112, in turn, has a heavier dopant concentration than p− substrate 110.
As further shown in FIG. 1, semiconductor die 100 additionally includes an NMOS transistor 120 and a PMOS transistor 130. NMOS transistor 120 has spaced-apart n+ source and drain regions 122 and 124 that are formed in p− well 112, and a p− channel region 126 that lies between and contacts source and drain regions 122 and 124. NMOS transistor 120 also has a gate oxide layer 128 that is formed on p− well 112 over channel region 126, and a gate G1 that is formed on gate oxide layer 128 over channel region 126.
PMOS transistor 130 has spaced-apart p+ source and drain regions 132 and 134 that are formed in n− well 114, and an n− channel region 136 that lies between and contacts source and drain regions 132 and 134. PMOS transistor 130 also has a gate oxide layer 138 that is formed on n− well 114 over channel region 136, and a gate G2 that is formed on gate oxide layer 138 over channel region 136.
As additionally shown in FIG. 1, die 100 has a conventional interconnect structure that includes a first dielectric layer 150 that is formed on top surface a 110A of substrate 110 over n+ regions 122 and 124, p+ regions 132 and 134, and gates G1 and G2. Further, a large number of contacts 152 are formed through first dielectric layer 150 to make electrical connections with n+ regions 122 and 124, p+ regions 132 and 134, and gates G1 and G2.
The interconnect structure also includes a large number of metal-1 regions 156, such as traces and lines, that are formed on first dielectric layer 150 to make electrical connections with the contacts 152, and a second dielectric layer 160 that is formed on first dielectric layer 150 and the metal-1 regions 156.
In addition, a large number of vias 162 are formed through second dielectric layer 160 to make electrical connections with the metal-1 regions 156, a large number of metal-2 regions 164, such as traces and lines, are formed on second dielectric layer 160 to make electrical connections with the vias 162, and a top dielectric layer 170 is formed on second dielectric layer 160 and the metal-2 regions 164.
To remove heat, semiconductor die 100 additionally includes a number of heat pipes 180 that are formed in substrate 110 to extend from the bottom surface of substrate 110 up into the wells 112 and 114, without touching the top surface of the wells 112 and 114. Each heat pipe 180 can include a metal region 182, such as metal silicide or other metallic materials and combinations, and an electrically isolating material 184, such as oxide, that only partially surrounds metal region 182. Metal region 182 has a side wall 182A and an end or top wall 182B. Isolating material 184, in turn, contacts side wall 182A, which isolates side wall 182A from substrate 110. Isolating material 184, however, does not contact top wall 182B.
In addition, die 100 can include a number of contact regions 186 that are formed in the wells 112 and 114 to correspond with the heat pipes 180. Each contact region 186 contacts the top wall 182B of a heat pipe 180, and has the same conductivity type, but a greater dopant concentration, than the adjoining well.
As further shown in FIG. 1, semiconductor die 100 also includes a number of heat pipes 190 that are formed to extend up from the bottom surface into p− substrate 110. Heat pipes 190 are identical to heat pipes 180 except that heat pipes 190 are shorter and extend into only p− substrate 110. Thus, as above, each heat pipe 190 can include a metal region 192, such as metal silicide or other metallic materials and combinations, and an electrically isolating material 194, such as oxide, that only partially surrounds metal region 192. Metal region 192 has a side wall 192A and an end or top wall 192B. Isolating material 194, in turn, contacts side wall 192A, which isolates side wall 192A from substrate 110. Isolating material 194, however, does not contact top wall 192B.
In addition, semiconductor die 100 can include a number of contact regions 196 that are formed in substrate 110 to correspond with the heat pipes 190. Each contact region 196 contacts the top wall 192B, and has the same conductivity type, but a greater dopant concentration than, the adjoining region of substrate 110.
In operation, significant amounts of heat can be generated in the channel regions 126 and 136 when transistors 120 and 130 are high current transistors, such as driver transistors. Heat pipes 180 and 190, in turn, provide a thermal path that reduces the build up of heat in substrate 110. (Pipes 180 and 190 also provide a means for setting the voltage on p− substrate 110, p− well 112, and n− well 114.)
Although heat pipes 180 and 190 reduce the build up of heat in the high-current regions of the substrate, there is a need for additional approaches to removing heat from the high-current regions of the substrate.